(1) Field of the Invention
The present invention relates to a skew adjusting circuit and method for parallel signals. The invention relates to technology suitable for use in phase matching among parallel signals when a high-speed signal at a bit rate of, e.g., 40 Gb/s is transmitted as parallel signals of 10 Gb/s×4 channels.
(2) Description of the Related Art
Recently, in optical communication systems, the volume of transmission has been raised by increasing the bit rate. In apparatuses in optical communication systems, when signal transmission is performed between various modules, ICs (Integrated Circuits), and LSIs (Large Scale Integrations), etc., a signal is made into parallel signals to reduce the speed, thereby making signal processing by low-speed devices possible. Since the transmission speed of each channel is lowered when the number of signals paralleled is increased, the high-speed characteristics required in the devices are reduced, and phase matching among parallel signals becomes easy to obtain. However, problems of increase in the numbers of ICs, LSIs, pins of modules, in the package size, and in the packaging area of transmission lines arise.
Today, as a method for parallel transmission of a signal at a bit rate of 40 Gb/s, the scheme of SFI (Serdes Framer Interface)-5, in which 2.5 Gb/s×16 channels are transmitted, is standardized by the OIF (Optical Internetworking Forum). This SFI-5 is a scheme which is based on the assumption that phase shift is caused in transceiving interfaces and transmission paths, and it includes a deskew circuit for restoring the phase.
FIG. 12 is a block diagram showing a construction of a 40 Gb/s transponder module in conformity with SFI-5; FIG. 13 is a block diagram showing a construction with attention paid to the transmitter-end interface (IF) and the receiver-end interface (IF) of FIG. 12.
First of all, as shown in FIG. 12, the transponder module includes: a framer (or FEC) 100 having a transmitter-end IF 101 and a receiver-end IF 102 in conformity with SFI-5; and a transponder unit 200. The transponder unit 200 includes: serializer/deserializer (SERDES) unit 208 having a receiver-end IF 201 and a transmitter-end IF 206 which are in conformity with SFI-5, a 16:1 multiplexing (MUX) circuit 202; a clock data recovery (CDR)/1:16 demultiplexing (DMUX) circuit 205; an electric/optic converter unit 203; optic/electric converter unit 204; and a CPU 207.
In such a construction, a data signal (main signal) at a bit rate of 40 Gb/s is transceived in the form of parallel signals of 2.5 Gb/s×16 channels, together with a deskew signal of 2.5 Gb/s×1 channel, between the transmitter-end IF 101 of the framer 100 and the receiver-end IF 201 of the transponder unit 200 (SERDES unit 208), and between the transmitter-end IF 206 of the transponder unit 200 (SERDES unit 208) and the receiver-end IF 102 of the framer 100 (that is, a total of 2.5 Gb/s×17 channels, including a 2.5 Gb/s deskew channel, are transceived in parallel).
The parallel data signals of 2.5 Gb/s×16 channels received by the receiver-end IF 201 are subjected to phase shift (skew) detection between data signals of the different channels. The skew detection and compensation are performed using the above-mentioned deskew signal from the transmitter-end IF 101. The resultant signals are multiplexed by the MUX circuit 202 into a serial signal at a bit rate of 40 Gb/s, and are then converted into an optical signal at a bit rate of 40 Gb/s. After that the optical signal is sent out onto an optical transmission path (optical fiber) 300.
On the other hand, an optical signal at a bit rate of 40 Gb/s transmitted from the opposite optical transmission path 400 is converted by the optic/electric converter unit 204 into an electrical signal at a bit rate of 40 Gb/s. After that, the electrical signal is subjected to clock and data recovery processing performed by the CDR/DMUX circuit 205. The resultant signal is converted into parallel signals of 2.5 Gb/s×16 channels, and is then sent out by the transmitter-end IF 206 to the receiver-end IF 102 of the framer 100 in the form of 17 parallel signals including a 2.5 Gb×1 channel deskew signal. On the receiver-end IF 102, like the receiver-end IF 201, skew between the 16 parallel data signals is detected and compensated for using the deskew signal from the transmitter-end IF 206. In this instance, the operation of the above electric/optic converter unit 203, optic/electric converter unit 204, MUX circuit 202, and CDR/DMUX circuit 205 is integratedly monitored and controlled by the CPU 207.
As described so far, in the above-described transponder module, skew among parallel signals of 16 channels transmitted between the transmitter-end IF 101 (206) and the receiver-end IF 201 (102), is detected and compensated for by using a deskew signal. Thus, as shown in FIG. 13, the deskew signal generating circuit 500 is provided for the transmitter-end IF 101 (206), and the deskew circuit 600 is provided for the receiver-end IF 201 (102).
In more detail, the transmitter-end IF 101 (206) includes a framing controller 501, a 16:1 multiplexing (MUX) circuit 502, and a selector 503, which serve as the deskew signal generating circuit 500. The transmitter-end IF 101 (206) also includes a core logic circuit 510 for outputting data signals of 2.5 Gb×16 channels and buffers 511, providing one for each of the parallel data signals. The receiver-end IF 201 (102) includes: a data recovery (DR) circuit 601 and a buffer 602, which are provided for a deskew signal; DR circuits 603, buffers 604, and variable delay circuits 605, which are provided, one for each of the data signals on 16 channels; a multiplexing (MUX) circuit 606 (equivalent to the MUX circuit 202 of FIG. 12) for multiplexing and outputting the parallel signals on the 16 channels; a deskew controller 607 for compensating for skew among the parallel data signals by controlling the delay amount of each of the variable delay circuit 605. Here, a block including the variable delay circuits 605 and deskew controller 607 functions as the above-mentioned deskew circuit 600.
In the transmitter-end IF 101 (206) with the above construction, parallel data signals of 2.5 Gb/s×16 channels are output from the core logic circuit 510. After being temporarily held in buffers 511, the signals are then transmitted to the receiver-end IF 201. Here, according to SFI-5, design is performed so that output skew among channels from the transmitter-end IF 101 (206) is within 3 UIs (Unit Intervals) [1 UI=1 bit (400 pico seconds)].
In this instance, a part of the output of each buffer 511 is split to be input to the 1:16 multiplexing unit 502. Under control of the framing controller 501, the split signals are selectively output to the selector 503. The selector 503 selectively outputs the split signal or a signal from the framing controller 501, thereby generating a deskew signal with a predetermined frame format.
More precisely, the frame format of a deskew signal according to SFI-5 has 1088 bits per frame, as shown in FIG. 14. Using the leading 1st through 32nd bits (4 bytes), A1 byte (11110110) and A2 byte (00101000), which are frame synchronization patterns, are transmitted. Using the 65th through 128th bits (64 bits/8 bytes), a data signal of the channel number #15, out of the channel number #0 through #15, is transmitted. Using the 129th through 192nd bits (64 bits/8 bytes), a data signal of the channel number #14 is transmitted. Likewise, using the 193rd through 1088th bits, data signals of the channel number #13 through #0 are transmitted. Here, the 33rd through the 64th bits (four bytes) are defined to be an expansion header for future use.
By transmitting the deskew signal with such a frame format, together with 16-channel parallel signals, the receiver-end IF 201 (102) detects the above frame synchronization pattern (A1 and A2 bytes) of the deskew signal, thereby uniquely defining the placement (that is, reception timing) of the data signal on each channel. At this timing, successive pattern matching in 8-byte (64-bit) units is performed, whereby skew among the channels is detected.
That is, on the receiver-end IF 201 (102), the deskew signal, generated and transmitted from the transmitter-end IF 101 (206), is subjected to data recovery processing by a DR circuit 601. After being temporarily held in the buffer 602, the deskew signal is input to the deskew controller 607.
The deskew controller 607 detects the above-mentioned frame synchronization pattern (A1 and A2 bytes) of the deskew signal, thereby confirming the placement (reception timing) of the data signal of each channel. At this timing, like the above deskew signal, parallel data signals on 16 channels, after being subjected to data recovery processing by the DR circuit 603 and temporarily held in the buffer 64, are subjected to successive pattern matching in 8-byte (64-bit) units, whereby skew among the channels is detected.
After that, the deskew controller 607 individually controls the delay amounts of the variable delay circuits 605 so that skew disappears, thereby compensating for the skew among the parallel signals of 16 channels. Here, according to SFI-5, design is performed so that input permission skew on the receiver-end IF 201 (102) is within 6 UI (that is, skew within 6 UI can be compensated for).
Then, after compensation for the skew among the channels, the parallel data signals are multiplexed into a serial signal by MUX circuit 606 (202), and are then output as a signal at a bit rate of 40 Gb/s.
In this instance, as a circuit for adjusting skew among data bits, there is an art (hereinafter will be called publicly known art 1) disclosed in the following patent document 1. In this publicly known art 1, skew is adjusted on the receiver end based on a pseudo random pattern (PN pattern) produced on the transmitter end. This art is considered to be an art in which a PN pattern is used in place of a deskew signal.
Further, there is an art (hereinafter will be called publicly known art 2) proposed in the patent document 2 as a data capturing technique for high-speed signaling which makes possible the optimum sampling of non-synchronized data stream. This publicly known art 2 uses a delayed signal (delay tap output) of an original signal as a history record. This history record is tested, whereby optimum sampling is available.
[Patent Document 1] Japanese Patent Application Laid-open No. HEI 10-164037
[Patent Document 2] Published Japanese Translation of PCT application, No. 2004-531117
However, in the transponder module in conformity with SFI-5, the circuit size of the deskew signal generating circuit 500 and the deskew circuit 600, which performs deskew processing based on the generated deskew signal is large, so that power consumption and the circuit size are increased.
In particular, in the transponder 200, a high-speed characteristic is needed by the MUX circuit 202 (606) and the DMUX circuit 205, which are conversion circuits between parallel signals and a serial signal having an optical transmission speed, and the deskew circuit 600 is also needed. Therefore, realizing these points is a problem that needs solving. That is, according to previous technology, for realizing deskew, a logic circuit with hundreds to thousands of gates is needed, and realizing this with circuits superior in speed is extremely difficult due to power consumption and circuit size.
Further, as a next generation scheme, transmission of parallel signals of 10 Gb/s×4 channels is under consideration. Thus, power consumption and circuit size with respect to the MUX circuit 202 (606) and the DMUX circuit 205 become highly problematic. Here, simple application of the above publicly known arts 1 and 2 won't solve the problem unique to the transponder module in which high-speed characteristics are needed.